XILINX ASIA PACIFIC PTE. LTD.
Senior DFT Engineer
Roles & Responsibilities
- Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
- Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
- Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, 1149.1 JTAG and IJTAG
- Assist in Diagnosis and Yield enhancement through product lifecycle
- BS/MS EE with relevant logic design/test background. 3-5 years’ work experience as a DFT engineer.
- Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
- Proficient in logic design using Verilog and experience in synthesis and STA
- Experience in developing test benches and simulation in RTL/GATE/SDF environments
- Good communication skill and has to be able to works well in a group environment that spans across continents
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay), scan compression. Knowledge of MBIST is a plus.
- Knowledge of FPGA synthesis and design flow is a plus
- Perl, shell scripting skills as well as Linux OS environment are assumed.
FOR MORE DETAILS PLEASE CONTACT firstname.lastname@example.org